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Lattice Semiconductor
PCI Express User’s Guide
? CRC error for Normal TLP
? If CRC is ok and received Sequence of the TLP violates the condition
(NEXT_RCV_SEQ - Sequence Number) mod 4096 ≤ 2048
The core will discard this Bad TLP and reply with a NAK DLLP. Error signal bad_tlp will be asserted to notify the
user logic.
Bad DLLP
This error signal is generated to indicate that the received DLLP is erroneous when there is no rx_err signal from
the Electrical Sub Block of the Physical Layer. The condition that leads to asserting this signal is listed below:
? CRC error in the received DLLP
The core will discard this Bad DLLP and error signal bad_dllp will be asserted to notify the user logic.
Data Link Layer Protocol Error
The Data Link Layer Protocol Error is generated for the following conditions in a received DLLP:
? If ((NEXT_TRANSMIT_SEQ - 1) - AckNak_Seq_Num) mod 4096 > 2048, or
? If the above error condition is not noticed, but (ACKNak_Seq_Num - ACKD_SEQ) mod 4096 => 2048
Refer to Figures 3-17 in the PCI Express Speci?cation 1.0a for more details.
The core will discard this DLLP and error signal dll_perr will be asserted to notify the user logic
Replay Number Rollover
The Replay Number Rollover status signal is a pulse of one clock duration and is generated when the internal
replay number changes from 3 to 4.
The core asserts the user interface signal rnum_rlor to indicate this rollover.
Replay Timeout
The Replay time is the time between transmission of the last DWORD of a TLP and reception of the ?rst DWORD of
an ACK/NACK DLLP for that TLP.
The timer is restarted for any of the following conditions:
? When a DLLP is received and the retry buffer has some of the un-acknowledged TLPs
? At the beginning of a TLP transmission if the timer is not running
? At the expiration of the timer value.
The core asserts the user interface signal rply_tout to indicate this timeout.
More details on all these error signals are available in the Timing Diagram section.
User Logic Interface
Transmit User Interface
All transactions initiated from the User Interface side are synchronized with the rising edge of div2_pclk . Trans-
actions between the core and the user interface logic are carried out in the form of TLPs.
Tx TLPs are loaded into the core through a 32-bit data bus, txtlpu_data . The following handshake signals are
provided to ensure a smooth and controlled interface between the core and the user Interface logic:
txtplu_req – User interface logic asserts this input signal to request a transmission of TLP.
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